When a circuit is formed on a surface of a semiconductor wafer to manufacture a semiconductor device, if flatness of the surface of the semiconductor wafer is low, focusing during exposure is partially inaccurate in photolithography steps for forming the circuit, which can affect the formation of a fine pattern of the circuit. Therefore, the surface and the back surface of the semiconductor wafer require remarkably high flatness.
In order to achieve the remarkably high flatness of the surface and the back surface of the semiconductor wafer, the surface and the back surface of the semiconductor wafer need to be polished with high accuracy, and a double side polishing apparatus is known therefor. The double side polishing apparatus polishes the surface and the back surface of the semiconductor wafer at the same time by relative movement between polishing pads provided on surface plates and the semiconductor wafer held in a carrier.
In the double side polishing apparatus, when the thickness of the semiconductor wafer to be polished is larger than the thickness of the carrier, the semiconductor wafer lies between the polishing pads and thus the polishing of the outer periphery of the semiconductor wafer is excessively promoted. Consequently, droop occurs at the outer periphery (edge) of the surface and the back surface of the semiconductor wafer and the flatness of the semiconductor wafer may be deteriorated.
In order to prevent the droop at the outer periphery, there is disclosed in Patent Document 1 a technique for setting the thickness of the carrier to be substantially matched with a target value of the final thickness of the semiconductor wafer and distributing a surface pressure acting on the outer periphery of the semiconductor wafer from the polishing pads over the carrier, thereby preventing the droop at the outer periphery of the semiconductor wafer.
However, even by the double side polishing apparatus which adjusts the thickness of the carrier as described above, the center of the polished semiconductor wafer may be concave to be largely depressed or may be convex to be largely expanded due to the shape of the surface plates or an influence by an applied state of the polishing pads provided on the surface plates and thus the flatness of the surface and the back surface of the polished semiconductor wafer cannot achieve a desired value.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-235941